#ifndef XPARAMETERS_H   /* prevent circular inclusions */
#define XPARAMETERS_H   /* by using protection macros */

/* Definitions for bus frequencies */
#define XPAR_CPU_M_AXI_DP_FREQ_HZ 100000000
#define XPAR_CPU_M_AXI_IP_FREQ_HZ 100000000
/******************************************************************/

/* Canonical definitions for bus frequencies */
#define XPAR_PROC_BUS_0_FREQ_HZ 100000000
#define XPAR_PROC_BUS_1_FREQ_HZ 100000000
/******************************************************************/

#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 100000000
#define XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ 100000000

/******************************************************************/


/* Definitions for peripheral MICROBLAZE_PS */
#define XPAR_MICROBLAZE_PS_ADDR_SIZE 32
#define XPAR_MICROBLAZE_PS_ADDR_TAG_BITS 16
#define XPAR_MICROBLAZE_PS_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_PS_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_PS_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_PS_ASYNC_INTERRUPT 1
#define XPAR_MICROBLAZE_PS_ASYNC_WAKEUP 3
#define XPAR_MICROBLAZE_PS_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_PS_BASE_VECTORS 0x0000000000000000
#define XPAR_MICROBLAZE_PS_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_PS_CACHE_BYTE_SIZE 8192
#define XPAR_MICROBLAZE_PS_DADDR_SIZE 32
#define XPAR_MICROBLAZE_PS_DATA_SIZE 32
#define XPAR_MICROBLAZE_PS_DCACHE_ADDR_TAG 16
#define XPAR_MICROBLAZE_PS_DCACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_PS_DCACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_PS_DCACHE_BYTE_SIZE 8192
#define XPAR_MICROBLAZE_PS_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_PS_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_PS_DCACHE_HIGHADDR 0x9FFFFFFF
#define XPAR_MICROBLAZE_PS_DCACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_PS_DCACHE_USE_WRITEBACK 1
#define XPAR_MICROBLAZE_PS_DCACHE_VICTIMS 0
#define XPAR_MICROBLAZE_PS_DC_AXI_MON 0
#define XPAR_MICROBLAZE_PS_DEBUG_COUNTER_WIDTH 32
#define XPAR_MICROBLAZE_PS_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_PS_DEBUG_EVENT_COUNTERS 5
#define XPAR_MICROBLAZE_PS_DEBUG_EXTERNAL_TRACE 0
#define XPAR_MICROBLAZE_PS_DEBUG_INTERFACE 0
#define XPAR_MICROBLAZE_PS_DEBUG_LATENCY_COUNTERS 1
#define XPAR_MICROBLAZE_PS_DEBUG_PROFILE_SIZE 0
#define XPAR_MICROBLAZE_PS_DEBUG_TRACE_ASYNC_RESET 0
#define XPAR_MICROBLAZE_PS_DEBUG_TRACE_SIZE 8192
#define XPAR_MICROBLAZE_PS_DIV_ZERO_EXCEPTION 1
#define XPAR_MICROBLAZE_PS_DP_AXI_MON 0
#define XPAR_MICROBLAZE_PS_DYNAMIC_BUS_SIZING 0
#define XPAR_MICROBLAZE_PS_D_AXI 1
#define XPAR_MICROBLAZE_PS_D_LMB 1
#define XPAR_MICROBLAZE_PS_D_LMB_MON 0
#define XPAR_MICROBLAZE_PS_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_PS_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_PS_ENABLE_DISCRETE_PORTS 0
#define XPAR_MICROBLAZE_PS_ENDIANNESS 1
#define XPAR_MICROBLAZE_PS_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_PS_FPU_EXCEPTION 0
#define XPAR_MICROBLAZE_PS_FREQ 100000000
#define XPAR_MICROBLAZE_PS_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_PS_FSL_LINKS 0
#define XPAR_MICROBLAZE_PS_IADDR_SIZE 32
#define XPAR_MICROBLAZE_PS_ICACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_PS_ICACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_PS_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_PS_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_PS_ICACHE_HIGHADDR 0x9FFFFFFF
#define XPAR_MICROBLAZE_PS_ICACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_PS_ICACHE_STREAMS 0
#define XPAR_MICROBLAZE_PS_ICACHE_VICTIMS 0
#define XPAR_MICROBLAZE_PS_IC_AXI_MON 0
#define XPAR_MICROBLAZE_PS_ILL_OPCODE_EXCEPTION 1
#define XPAR_MICROBLAZE_PS_IMPRECISE_EXCEPTIONS 0
#define XPAR_MICROBLAZE_PS_INSTR_SIZE 32
#define XPAR_MICROBLAZE_PS_INTERCONNECT 2
#define XPAR_MICROBLAZE_PS_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_PS_INTERRUPT_MON 0
#define XPAR_MICROBLAZE_PS_IP_AXI_MON 0
#define XPAR_MICROBLAZE_PS_I_AXI 1
#define XPAR_MICROBLAZE_PS_I_LMB 1
#define XPAR_MICROBLAZE_PS_I_LMB_MON 0
#define XPAR_MICROBLAZE_PS_LOCKSTEP_MASTER 0
#define XPAR_MICROBLAZE_PS_LOCKSTEP_SELECT 0
#define XPAR_MICROBLAZE_PS_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_PS_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_MMU_DTLB_SIZE 2
#define XPAR_MICROBLAZE_PS_MMU_ITLB_SIZE 1
#define XPAR_MICROBLAZE_PS_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_PS_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_PS_MMU_ZONES 2
#define XPAR_MICROBLAZE_PS_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_PS_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_PS_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_DC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_PS_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_DC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_PS_M_AXI_DC_USER_VALUE 31
#define XPAR_MICROBLAZE_PS_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_PS_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_D_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_PS_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_PS_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_PS_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_IC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_IC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_PS_M_AXI_IC_USER_VALUE 31
#define XPAR_MICROBLAZE_PS_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_PS_M_AXI_I_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_PS_NUMBER_OF_PC_BRK 2
#define XPAR_MICROBLAZE_PS_NUMBER_OF_RD_ADDR_BRK 0
#define XPAR_MICROBLAZE_PS_NUMBER_OF_WR_ADDR_BRK 0
#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_CLK 2
#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_CLK_DEBUG 2
#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_CLK_IRQ 1
#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_DBG_CLK 1
#define XPAR_MICROBLAZE_PS_NUM_SYNC_FF_DBG_TRACE_CLK 2
#define XPAR_MICROBLAZE_PS_OPCODE_0X0_ILLEGAL 1
#define XPAR_MICROBLAZE_PS_OPTIMIZATION 0
#define XPAR_MICROBLAZE_PS_PC_WIDTH 32
#define XPAR_MICROBLAZE_PS_PIADDR_SIZE 32
#define XPAR_MICROBLAZE_PS_PVR 0
#define XPAR_MICROBLAZE_PS_PVR_USER1 0x00
#define XPAR_MICROBLAZE_PS_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_PS_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_PS_RESET_MSR_BIP 0
#define XPAR_MICROBLAZE_PS_RESET_MSR_DCE 0
#define XPAR_MICROBLAZE_PS_RESET_MSR_EE 0
#define XPAR_MICROBLAZE_PS_RESET_MSR_EIP 0
#define XPAR_MICROBLAZE_PS_RESET_MSR_ICE 0
#define XPAR_MICROBLAZE_PS_RESET_MSR_IE 0
#define XPAR_MICROBLAZE_PS_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_PS_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_PS_SCO 0
#define XPAR_MICROBLAZE_PS_TRACE 0
#define XPAR_MICROBLAZE_PS_UNALIGNED_EXCEPTIONS 1
#define XPAR_MICROBLAZE_PS_USE_BARREL 1
#define XPAR_MICROBLAZE_PS_USE_BRANCH_TARGET_CACHE 0
#define XPAR_MICROBLAZE_PS_USE_CONFIG_RESET 0
#define XPAR_MICROBLAZE_PS_USE_DCACHE 1
#define XPAR_MICROBLAZE_PS_USE_DIV 1
#define XPAR_MICROBLAZE_PS_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_PS_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_PS_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_PS_USE_FPU 0
#define XPAR_MICROBLAZE_PS_USE_HW_MUL 1
#define XPAR_MICROBLAZE_PS_USE_ICACHE 1
#define XPAR_MICROBLAZE_PS_USE_INTERRUPT 1
#define XPAR_MICROBLAZE_PS_USE_MMU 0
#define XPAR_MICROBLAZE_PS_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_PS_USE_NON_SECURE 0
#define XPAR_MICROBLAZE_PS_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_PS_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_PS_USE_STACK_PROTECTION 0
#define XPAR_MICROBLAZE_PS_COMPONENT_NAME microblaze_microblaze_0_0
#define XPAR_MICROBLAZE_PS_EDK_IPTYPE PROCESSOR
#define XPAR_MICROBLAZE_PS_EDK_SPECIAL microblaze
#define XPAR_MICROBLAZE_PS_G_TEMPLATE_LIST 9
#define XPAR_MICROBLAZE_PS_G_USE_EXCEPTIONS 1

/******************************************************************/

#define XPAR_CPU_ID 0
#define XPAR_MICROBLAZE_ID 0
#define XPAR_MICROBLAZE_ADDR_SIZE 32
#define XPAR_MICROBLAZE_ADDR_TAG_BITS 16
#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_ASYNC_INTERRUPT 1
#define XPAR_MICROBLAZE_ASYNC_WAKEUP 3
#define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_BASE_VECTORS 0x0000000000000000
#define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 8192
#define XPAR_MICROBLAZE_DADDR_SIZE 32
#define XPAR_MICROBLAZE_DATA_SIZE 32
#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 16
#define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 8192
#define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0x9FFFFFFF
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 1
#define XPAR_MICROBLAZE_DCACHE_VICTIMS 0
#define XPAR_MICROBLAZE_DC_AXI_MON 0
#define XPAR_MICROBLAZE_DEBUG_COUNTER_WIDTH 32
#define XPAR_MICROBLAZE_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_DEBUG_EVENT_COUNTERS 5
#define XPAR_MICROBLAZE_DEBUG_EXTERNAL_TRACE 0
#define XPAR_MICROBLAZE_DEBUG_INTERFACE 0
#define XPAR_MICROBLAZE_DEBUG_LATENCY_COUNTERS 1
#define XPAR_MICROBLAZE_DEBUG_PROFILE_SIZE 0
#define XPAR_MICROBLAZE_DEBUG_TRACE_ASYNC_RESET 0
#define XPAR_MICROBLAZE_DEBUG_TRACE_SIZE 8192
#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 1
#define XPAR_MICROBLAZE_DP_AXI_MON 0
#define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 0
#define XPAR_MICROBLAZE_D_AXI 1
#define XPAR_MICROBLAZE_D_LMB 1
#define XPAR_MICROBLAZE_D_LMB_MON 0
#define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_ENABLE_DISCRETE_PORTS 0
#define XPAR_MICROBLAZE_ENDIANNESS 1
#define XPAR_MICROBLAZE_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_FPU_EXCEPTION 0
#define XPAR_MICROBLAZE_FREQ 100000000
#define XPAR_MICROBLAZE_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_FSL_LINKS 0
#define XPAR_MICROBLAZE_IADDR_SIZE 32
#define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 1
#define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x80000000
#define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0x9FFFFFFF
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_ICACHE_STREAMS 0
#define XPAR_MICROBLAZE_ICACHE_VICTIMS 0
#define XPAR_MICROBLAZE_IC_AXI_MON 0
#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 1
#define XPAR_MICROBLAZE_IMPRECISE_EXCEPTIONS 0
#define XPAR_MICROBLAZE_INSTR_SIZE 32
#define XPAR_MICROBLAZE_INTERCONNECT 2
#define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 0
#define XPAR_MICROBLAZE_INTERRUPT_MON 0
#define XPAR_MICROBLAZE_IP_AXI_MON 0
#define XPAR_MICROBLAZE_I_AXI 1
#define XPAR_MICROBLAZE_I_LMB 1
#define XPAR_MICROBLAZE_I_LMB_MON 0
#define XPAR_MICROBLAZE_LOCKSTEP_MASTER 0
#define XPAR_MICROBLAZE_LOCKSTEP_SELECT 0
#define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_MMU_DTLB_SIZE 2
#define XPAR_MICROBLAZE_MMU_ITLB_SIZE 1
#define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_MMU_ZONES 2
#define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_M_AXI_DC_USER_VALUE 31
#define XPAR_MICROBLAZE_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_USER_SIGNALS 0
#define XPAR_MICROBLAZE_M_AXI_IC_USER_VALUE 31
#define XPAR_MICROBLAZE_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 1
#define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 2
#define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 0
#define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 0
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK 2
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_DEBUG 2
#define XPAR_MICROBLAZE_NUM_SYNC_FF_CLK_IRQ 1
#define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_CLK 1
#define XPAR_MICROBLAZE_NUM_SYNC_FF_DBG_TRACE_CLK 2
#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 1
#define XPAR_MICROBLAZE_OPTIMIZATION 0
#define XPAR_MICROBLAZE_PC_WIDTH 32
#define XPAR_MICROBLAZE_PIADDR_SIZE 32
#define XPAR_MICROBLAZE_PVR 0
#define XPAR_MICROBLAZE_PVR_USER1 0x00
#define XPAR_MICROBLAZE_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_RESET_MSR_BIP 0
#define XPAR_MICROBLAZE_RESET_MSR_DCE 0
#define XPAR_MICROBLAZE_RESET_MSR_EE 0
#define XPAR_MICROBLAZE_RESET_MSR_EIP 0
#define XPAR_MICROBLAZE_RESET_MSR_ICE 0
#define XPAR_MICROBLAZE_RESET_MSR_IE 0
#define XPAR_MICROBLAZE_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_SCO 0
#define XPAR_MICROBLAZE_TRACE 0
#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 1
#define XPAR_MICROBLAZE_USE_BARREL 1
#define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 0
#define XPAR_MICROBLAZE_USE_CONFIG_RESET 0
#define XPAR_MICROBLAZE_USE_DCACHE 1
#define XPAR_MICROBLAZE_USE_DIV 1
#define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_USE_EXT_BRK 0
#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 0
#define XPAR_MICROBLAZE_USE_FPU 0
#define XPAR_MICROBLAZE_USE_HW_MUL 1
#define XPAR_MICROBLAZE_USE_ICACHE 1
#define XPAR_MICROBLAZE_USE_INTERRUPT 1
#define XPAR_MICROBLAZE_USE_MMU 0
#define XPAR_MICROBLAZE_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_USE_NON_SECURE 0
#define XPAR_MICROBLAZE_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 0
#define XPAR_MICROBLAZE_COMPONENT_NAME microblaze_microblaze_0_0
#define XPAR_MICROBLAZE_EDK_IPTYPE PROCESSOR
#define XPAR_MICROBLAZE_EDK_SPECIAL microblaze
#define XPAR_MICROBLAZE_G_TEMPLATE_LIST 9
#define XPAR_MICROBLAZE_G_USE_EXCEPTIONS 1

/******************************************************************/

/* Platform specific definitions */
#define PLATFORM_MB
 
/******************************************************************/
#define STDIN_BASEADDRESS 0x40600000
#define STDOUT_BASEADDRESS 0x40600000

/******************************************************************/

/* Definitions for driver AXIDMA */
#define XPAR_XAXIDMA_NUM_INSTANCES 1

/* Definitions for peripheral AXI_DMA_0 */
#define XPAR_AXI_DMA_0_DEVICE_ID 0
#define XPAR_AXI_DMA_0_BASEADDR 0x41E00000
#define XPAR_AXI_DMA_0_HIGHADDR 0x41E0FFFF
#define XPAR_AXI_DMA_0_SG_INCLUDE_STSCNTRL_STRM 0
#define XPAR_AXI_DMA_0_INCLUDE_MM2S_DRE 1
#define XPAR_AXI_DMA_0_INCLUDE_S2MM_DRE 1
#define XPAR_AXI_DMA_0_INCLUDE_MM2S 1
#define XPAR_AXI_DMA_0_INCLUDE_S2MM 1
#define XPAR_AXI_DMA_0_M_AXI_MM2S_DATA_WIDTH 64
#define XPAR_AXI_DMA_0_M_AXI_S2MM_DATA_WIDTH 64
#define XPAR_AXI_DMA_0_INCLUDE_SG 0
#define XPAR_AXI_DMA_0_ENABLE_MULTI_CHANNEL 0
#define XPAR_AXI_DMA_0_NUM_MM2S_CHANNELS 1
#define XPAR_AXI_DMA_0_NUM_S2MM_CHANNELS 1
#define XPAR_AXI_DMA_0_MM2S_BURST_SIZE 8
#define XPAR_AXI_DMA_0_S2MM_BURST_SIZE 16
#define XPAR_AXI_DMA_0_MICRO_DMA 0
#define XPAR_AXI_DMA_0_ADDR_WIDTH 32
#define XPAR_AXI_DMA_0_SG_LENGTH_WIDTH 14


/******************************************************************/

/* Canonical definitions for peripheral AXI_DMA_0 */
#define XPAR_AXIDMA_0_DEVICE_ID XPAR_AXI_DMA_0_DEVICE_ID
#define XPAR_AXIDMA_0_BASEADDR 0x41E00000
#define XPAR_AXIDMA_0_SG_INCLUDE_STSCNTRL_STRM 0
#define XPAR_AXIDMA_0_INCLUDE_MM2S 1
#define XPAR_AXIDMA_0_INCLUDE_MM2S_DRE 1
#define XPAR_AXIDMA_0_M_AXI_MM2S_DATA_WIDTH 64
#define XPAR_AXIDMA_0_INCLUDE_S2MM 1
#define XPAR_AXIDMA_0_INCLUDE_S2MM_DRE 1
#define XPAR_AXIDMA_0_M_AXI_S2MM_DATA_WIDTH 64
#define XPAR_AXIDMA_0_INCLUDE_SG 0
#define XPAR_AXIDMA_0_ENABLE_MULTI_CHANNEL 0
#define XPAR_AXIDMA_0_NUM_MM2S_CHANNELS 1
#define XPAR_AXIDMA_0_NUM_S2MM_CHANNELS 1
#define XPAR_AXIDMA_0_MM2S_BURST_SIZE 8
#define XPAR_AXIDMA_0_S2MM_BURST_SIZE 16
#define XPAR_AXIDMA_0_MICRO_DMA 0
#define XPAR_AXIDMA_0_c_addr_width 32
#define XPAR_AXIDMA_0_c_sg_length_width 14


/******************************************************************/

/* Definitions for driver BRAM */
#define XPAR_XBRAM_NUM_INSTANCES 2U

/* Definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DATA_WIDTH 32U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_FAULT_INJECT 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_WRITE_ACCESS 2U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_BASEADDR 0x00000000U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_HIGHADDR 0x0000FFFFU
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU 
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU 


/* Definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID 1U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DATA_WIDTH 32U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_FAULT_INJECT 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_FAILING_REGISTERS 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_UE_FAILING_REGISTERS 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_STATUS_REGISTERS 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_CE_COUNTER_WIDTH 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_REGISTER 0U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_ECC_ONOFF_RESET_VALUE 1U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_WRITE_ACCESS 2U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_BASEADDR 0x00000000U
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_HIGHADDR 0x0000FFFFU
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_BASEADDR 0xFFFFFFFFU 
#define XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_S_AXI_CTRL_HIGHADDR 0xFFFFFFFFU 


/******************************************************************/

/* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR */
#define XPAR_BRAM_0_DEVICE_ID XPAR_MICROBLAZE_0_LOCAL_MEMORY_DLMB_BRAM_IF_CNTLR_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 32U
#define XPAR_BRAM_0_ECC 0U
#define XPAR_BRAM_0_FAULT_INJECT 0U
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 1U
#define XPAR_BRAM_0_WRITE_ACCESS 2U
#define XPAR_BRAM_0_BASEADDR 0x00000000U
#define XPAR_BRAM_0_HIGHADDR 0x0000FFFFU

/* Canonical definitions for peripheral MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR */
#define XPAR_BRAM_1_DEVICE_ID XPAR_MICROBLAZE_0_LOCAL_MEMORY_ILMB_BRAM_IF_CNTLR_DEVICE_ID
#define XPAR_BRAM_1_DATA_WIDTH 32U
#define XPAR_BRAM_1_ECC 0U
#define XPAR_BRAM_1_FAULT_INJECT 0U
#define XPAR_BRAM_1_CE_FAILING_REGISTERS 0U
#define XPAR_BRAM_1_UE_FAILING_REGISTERS 0U
#define XPAR_BRAM_1_ECC_STATUS_REGISTERS 0U
#define XPAR_BRAM_1_CE_COUNTER_WIDTH 0U
#define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0U
#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 1U
#define XPAR_BRAM_1_WRITE_ACCESS 2U
#define XPAR_BRAM_1_BASEADDR 0x00000000U
#define XPAR_BRAM_1_HIGHADDR 0x0000FFFFU


/******************************************************************/

/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 2

/* Definitions for peripheral AXI_GPIO_0 */
#define XPAR_AXI_GPIO_0_BASEADDR 0x40000000
#define XPAR_AXI_GPIO_0_HIGHADDR 0x4000FFFF
#define XPAR_AXI_GPIO_0_DEVICE_ID 0
#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 1
#define XPAR_AXI_GPIO_0_IS_DUAL 0


/* Definitions for peripheral AXI_GPIO_1 */
#define XPAR_AXI_GPIO_1_BASEADDR 0x40010000
#define XPAR_AXI_GPIO_1_HIGHADDR 0x4001FFFF
#define XPAR_AXI_GPIO_1_DEVICE_ID 1
#define XPAR_AXI_GPIO_1_INTERRUPT_PRESENT 1
#define XPAR_AXI_GPIO_1_IS_DUAL 0


/******************************************************************/

/* Canonical definitions for peripheral AXI_GPIO_0 */
#define XPAR_GPIO_0_BASEADDR 0x40000000
#define XPAR_GPIO_0_HIGHADDR 0x4000FFFF
#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
#define XPAR_GPIO_0_INTERRUPT_PRESENT 1
#define XPAR_GPIO_0_IS_DUAL 0

/* Canonical definitions for peripheral AXI_GPIO_1 */
#define XPAR_GPIO_1_BASEADDR 0x40010000
#define XPAR_GPIO_1_HIGHADDR 0x4001FFFF
#define XPAR_GPIO_1_DEVICE_ID XPAR_AXI_GPIO_1_DEVICE_ID
#define XPAR_GPIO_1_INTERRUPT_PRESENT 1
#define XPAR_GPIO_1_IS_DUAL 0


/******************************************************************/

/* Definitions for driver HWICAP */
#define XPAR_XHWICAP_NUM_INSTANCES 1

/* Definitions for peripheral AXI_HWICAP_0 */
#define XPAR_AXI_HWICAP_0_BASEADDR 0x40200000
#define XPAR_AXI_HWICAP_0_HIGHADDR 0x4020FFFF
#define XPAR_AXI_HWICAP_0_DEVICE_ID 0
#define XPAR_AXI_HWICAP_0_ICAP_DWIDTH 32
#define XPAR_AXI_HWICAP_0_MODE 0


/******************************************************************/

/* Canonical definitions for peripheral AXI_HWICAP_0 */
#define XPAR_HWICAP_0_DEVICE_ID XPAR_AXI_HWICAP_0_DEVICE_ID
#define XPAR_HWICAP_0_BASEADDR 0x40200000
#define XPAR_HWICAP_0_HIGHADDR 0x4020FFFF
#define XPAR_HWICAP_0_ICAP_DWIDTH 32
#define XPAR_HWICAP_0_MODE 0


/******************************************************************/

/* Definitions for driver IIC */
#define XPAR_XIIC_NUM_INSTANCES 1

/* Definitions for peripheral AXI_7417_IIC */
#define XPAR_AXI_7417_IIC_DEVICE_ID 0
#define XPAR_AXI_7417_IIC_BASEADDR 0x40800000
#define XPAR_AXI_7417_IIC_HIGHADDR 0x4080FFFF
#define XPAR_AXI_7417_IIC_TEN_BIT_ADR 0
#define XPAR_AXI_7417_IIC_GPO_WIDTH 1


/******************************************************************/

/* Canonical definitions for peripheral AXI_7417_IIC */
#define XPAR_IIC_0_DEVICE_ID XPAR_AXI_7417_IIC_DEVICE_ID
#define XPAR_IIC_0_BASEADDR 0x40800000
#define XPAR_IIC_0_HIGHADDR 0x4080FFFF
#define XPAR_IIC_0_TEN_BIT_ADR 0
#define XPAR_IIC_0_GPO_WIDTH 1


/******************************************************************/

#define XPAR_INTC_MAX_NUM_INTR_INPUTS 9
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_HAS_SIE 1
#define XPAR_XINTC_HAS_CIE 1
#define XPAR_XINTC_HAS_IVR 1
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1

/* Definitions for peripheral AXI_INTC_0 */
#define XPAR_AXI_INTC_0_DEVICE_ID 0
#define XPAR_AXI_INTC_0_BASEADDR 0x41200000
#define XPAR_AXI_INTC_0_HIGHADDR 0x4120FFFF
#define XPAR_AXI_INTC_0_KIND_OF_INTR 0xFFFFFF1E
#define XPAR_AXI_INTC_0_HAS_FAST 0
#define XPAR_AXI_INTC_0_IVAR_RESET_VALUE 0x00000010
#define XPAR_AXI_INTC_0_NUM_INTR_INPUTS 9


/******************************************************************/

#define XPAR_INTC_SINGLE_BASEADDR 0x41200000
#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID
#define XPAR_AXI_INTC_0_TYPE 0U
#define XPAR_AXI_TIMER_0_INTERRUPT_MASK 0X000001U
#define XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR 0U
#define XPAR_AXI_SPI_IP2INTC_IRPT_MASK 0X000002U
#define XPAR_AXI_INTC_0_AXI_SPI_IP2INTC_IRPT_INTR 1U
#define XPAR_AXI_7417_IIC_IIC2INTC_IRPT_MASK 0X000004U
#define XPAR_AXI_INTC_0_AXI_7417_IIC_IIC2INTC_IRPT_INTR 2U
#define XPAR_AXI_DEBUG_UART_INTERRUPT_MASK 0X000008U
#define XPAR_AXI_INTC_0_AXI_DEBUG_UART_INTERRUPT_INTR 3U
#define XPAR_AXI_EXT_UART_INTERRUPT_MASK 0X000010U
#define XPAR_AXI_INTC_0_AXI_EXT_UART_INTERRUPT_INTR 4U
#define XPAR_AXI_DMA_0_MM2S_INTROUT_MASK 0X000020U
#define XPAR_AXI_INTC_0_AXI_DMA_0_MM2S_INTROUT_INTR 5U
#define XPAR_AXI_DMA_0_S2MM_INTROUT_MASK 0X000040U
#define XPAR_AXI_INTC_0_AXI_DMA_0_S2MM_INTROUT_INTR 6U
#define XPAR_AXI_GPIO_0_IP2INTC_IRPT_MASK 0X000080U
#define XPAR_AXI_INTC_0_AXI_GPIO_0_IP2INTC_IRPT_INTR 7U
#define XPAR_AXI_GPIO_1_IP2INTC_IRPT_MASK 0X000100U
#define XPAR_AXI_INTC_0_AXI_GPIO_1_IP2INTC_IRPT_INTR 8U

/******************************************************************/

/* Canonical definitions for peripheral AXI_INTC_0 */
#define XPAR_INTC_0_DEVICE_ID XPAR_AXI_INTC_0_DEVICE_ID
#define XPAR_INTC_0_BASEADDR 0x41200000U
#define XPAR_INTC_0_HIGHADDR 0x4120FFFFU
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFF1EU
#define XPAR_INTC_0_HAS_FAST 0U
#define XPAR_INTC_0_IVAR_RESET_VALUE 0x00000010U
#define XPAR_INTC_0_NUM_INTR_INPUTS 9U
#define XPAR_INTC_0_INTC_TYPE 0U

#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_AXI_INTC_0_AXI_TIMER_0_INTERRUPT_INTR
#define XPAR_INTC_0_SPI_1_VEC_ID XPAR_AXI_INTC_0_AXI_SPI_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_AXI_INTC_0_AXI_7417_IIC_IIC2INTC_IRPT_INTR
#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_AXI_INTC_0_AXI_DEBUG_UART_INTERRUPT_INTR
#define XPAR_INTC_0_UARTLITE_1_VEC_ID XPAR_AXI_INTC_0_AXI_EXT_UART_INTERRUPT_INTR
#define XPAR_INTC_0_AXIDMA_0_MM2S_INTROUT_VEC_ID XPAR_AXI_INTC_0_AXI_DMA_0_MM2S_INTROUT_INTR
#define XPAR_INTC_0_AXIDMA_0_S2MM_INTROUT_VEC_ID XPAR_AXI_INTC_0_AXI_DMA_0_S2MM_INTROUT_INTR
#define XPAR_INTC_0_GPIO_0_VEC_ID XPAR_AXI_INTC_0_AXI_GPIO_0_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_GPIO_1_VEC_ID XPAR_AXI_INTC_0_AXI_GPIO_1_IP2INTC_IRPT_INTR

/******************************************************************/

/* Definitions for driver MIG_7SERIES */
#define XPAR_XMIG7SERIES_NUM_INSTANCES 1U

/* Definitions for peripheral MIG_7SERIES_0 */
#define XPAR_MIG_7SERIES_0_DEVICE_ID 0U
#define XPAR_MIG_7SERIES_0_DDR3_ROW_WIDTH 15U
#define XPAR_MIG_7SERIES_0_DDR3_COL_WIDTH 0U
#define XPAR_MIG_7SERIES_0_DDR3_BANK_WIDTH 3U
#define XPAR_MIG_7SERIES_0_DDR3_DQ_WIDTH 16U


/******************************************************************/


/* Definitions for peripheral MIG_7SERIES_0 */
#define XPAR_MIG_7SERIES_0_BASEADDR 0x80000000
#define XPAR_MIG_7SERIES_0_HIGHADDR 0x9FFFFFFF


/******************************************************************/

/* Canonical definitions for peripheral MIG_7SERIES_0 */
#define XPAR_MIG7SERIES_0_DEVICE_ID XPAR_MIG_7SERIES_0_DEVICE_ID
#define XPAR_MIG7SERIES_0_DDR_ROW_WIDTH 15U
#define XPAR_MIG7SERIES_0_DDR_COL_WIDTH 0U
#define XPAR_MIG7SERIES_0_DDR_BANK_WIDTH 3U
#define XPAR_MIG7SERIES_0_DDR_DQ_WIDTH 16U
#define XPAR_MIG7SERIES_0_BASEADDR 0x80000000U
#define XPAR_MIG7SERIES_0_HIGHADDR 0x9FFFFFFFU


/******************************************************************/

/* Definitions for driver SPI */
#define XPAR_XSPI_NUM_INSTANCES 2U

/* Definitions for peripheral AXI_QUAD_SPI_0 */
#define XPAR_AXI_QUAD_SPI_0_DEVICE_ID 0U
#define XPAR_AXI_QUAD_SPI_0_BASEADDR 0x44A00000U
#define XPAR_AXI_QUAD_SPI_0_HIGHADDR 0x44A0FFFFU
#define XPAR_AXI_QUAD_SPI_0_FIFO_DEPTH 16U
#define XPAR_AXI_QUAD_SPI_0_FIFO_EXIST 1U
#define XPAR_AXI_QUAD_SPI_0_SPI_SLAVE_ONLY 0U
#define XPAR_AXI_QUAD_SPI_0_NUM_SS_BITS 1U
#define XPAR_AXI_QUAD_SPI_0_NUM_TRANSFER_BITS 8U
#define XPAR_AXI_QUAD_SPI_0_SPI_MODE 2U
#define XPAR_AXI_QUAD_SPI_0_TYPE_OF_AXI4_INTERFACE 0U
#define XPAR_AXI_QUAD_SPI_0_AXI4_BASEADDR 0U
#define XPAR_AXI_QUAD_SPI_0_AXI4_HIGHADDR 0U
#define XPAR_AXI_QUAD_SPI_0_XIP_MODE 0U

/* Canonical definitions for peripheral AXI_QUAD_SPI_0 */
#define XPAR_SPI_0_DEVICE_ID 0U
#define XPAR_SPI_0_BASEADDR 0x44A00000U
#define XPAR_SPI_0_HIGHADDR 0x44A0FFFFU
#define XPAR_SPI_0_FIFO_DEPTH 16U
#define XPAR_SPI_0_FIFO_EXIST 1U
#define XPAR_SPI_0_SPI_SLAVE_ONLY 0U
#define XPAR_SPI_0_NUM_SS_BITS 1U
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8U
#define XPAR_SPI_0_SPI_MODE 2U
#define XPAR_SPI_0_TYPE_OF_AXI4_INTERFACE 0U
#define XPAR_SPI_0_AXI4_BASEADDR 0U
#define XPAR_SPI_0_AXI4_HIGHADDR 0U
#define XPAR_SPI_0_XIP_MODE 0U
#define XPAR_SPI_0_USE_STARTUP 1U



/* Definitions for peripheral AXI_SPI */
#define XPAR_AXI_SPI_DEVICE_ID 1U
#define XPAR_AXI_SPI_BASEADDR 0x44A30000U
#define XPAR_AXI_SPI_HIGHADDR 0x44A3FFFFU
#define XPAR_AXI_SPI_FIFO_DEPTH 16U
#define XPAR_AXI_SPI_FIFO_EXIST 1U
#define XPAR_AXI_SPI_SPI_SLAVE_ONLY 0U
#define XPAR_AXI_SPI_NUM_SS_BITS 6U
#define XPAR_AXI_SPI_NUM_TRANSFER_BITS 8U
#define XPAR_AXI_SPI_SPI_MODE 0U
#define XPAR_AXI_SPI_TYPE_OF_AXI4_INTERFACE 0U
#define XPAR_AXI_SPI_AXI4_BASEADDR 0U
#define XPAR_AXI_SPI_AXI4_HIGHADDR 0U
#define XPAR_AXI_SPI_XIP_MODE 0U

/* Canonical definitions for peripheral AXI_SPI */
#define XPAR_SPI_1_DEVICE_ID 1U
#define XPAR_SPI_1_BASEADDR 0x44A30000U
#define XPAR_SPI_1_HIGHADDR 0x44A3FFFFU
#define XPAR_SPI_1_FIFO_DEPTH 16U
#define XPAR_SPI_1_FIFO_EXIST 1U
#define XPAR_SPI_1_SPI_SLAVE_ONLY 0U
#define XPAR_SPI_1_NUM_SS_BITS 6U
#define XPAR_SPI_1_NUM_TRANSFER_BITS 8U
#define XPAR_SPI_1_SPI_MODE 0U
#define XPAR_SPI_1_TYPE_OF_AXI4_INTERFACE 0U
#define XPAR_SPI_1_AXI4_BASEADDR 0U
#define XPAR_SPI_1_AXI4_HIGHADDR 0U
#define XPAR_SPI_1_XIP_MODE 0U
#define XPAR_SPI_1_USE_STARTUP 0U



/******************************************************************/

/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1U

/* Definitions for peripheral AXI_TIMER_0 */
#define XPAR_AXI_TIMER_0_DEVICE_ID 0U
#define XPAR_AXI_TIMER_0_BASEADDR 0x41C00000U
#define XPAR_AXI_TIMER_0_HIGHADDR 0x41C0FFFFU
#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000U


/******************************************************************/

/* Canonical definitions for peripheral AXI_TIMER_0 */
#define XPAR_TMRCTR_0_DEVICE_ID 0U
#define XPAR_TMRCTR_0_BASEADDR 0x41C00000U
#define XPAR_TMRCTR_0_HIGHADDR 0x41C0FFFFU
#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ

/******************************************************************/

/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 2

/* Definitions for peripheral AXI_DEBUG_UART */
#define XPAR_AXI_DEBUG_UART_BASEADDR 0x40600000
#define XPAR_AXI_DEBUG_UART_HIGHADDR 0x4060FFFF
#define XPAR_AXI_DEBUG_UART_DEVICE_ID 0
#define XPAR_AXI_DEBUG_UART_BAUDRATE 115200
#define XPAR_AXI_DEBUG_UART_USE_PARITY 0
#define XPAR_AXI_DEBUG_UART_ODD_PARITY 0
#define XPAR_AXI_DEBUG_UART_DATA_BITS 8


/* Definitions for peripheral AXI_EXT_UART */
#define XPAR_AXI_EXT_UART_BASEADDR 0x40610000
#define XPAR_AXI_EXT_UART_HIGHADDR 0x4061FFFF
#define XPAR_AXI_EXT_UART_DEVICE_ID 1
#define XPAR_AXI_EXT_UART_BAUDRATE 115200
#define XPAR_AXI_EXT_UART_USE_PARITY 0
#define XPAR_AXI_EXT_UART_ODD_PARITY 0
#define XPAR_AXI_EXT_UART_DATA_BITS 8


/******************************************************************/

/* Canonical definitions for peripheral AXI_DEBUG_UART */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_DEBUG_UART_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0x40600000
#define XPAR_UARTLITE_0_HIGHADDR 0x4060FFFF
#define XPAR_UARTLITE_0_BAUDRATE 115200
#define XPAR_UARTLITE_0_USE_PARITY 0
#define XPAR_UARTLITE_0_ODD_PARITY 0
#define XPAR_UARTLITE_0_DATA_BITS 8

/* Canonical definitions for peripheral AXI_EXT_UART */
#define XPAR_UARTLITE_1_DEVICE_ID XPAR_AXI_EXT_UART_DEVICE_ID
#define XPAR_UARTLITE_1_BASEADDR 0x40610000
#define XPAR_UARTLITE_1_HIGHADDR 0x4061FFFF
#define XPAR_UARTLITE_1_BAUDRATE 115200
#define XPAR_UARTLITE_1_USE_PARITY 0
#define XPAR_UARTLITE_1_ODD_PARITY 0
#define XPAR_UARTLITE_1_DATA_BITS 8


/******************************************************************/

#endif  /* end of protection macro */
